Network Processor Design Volume 3 Issues and Practices 1st Edition by Mark Franklin, Peter Onufryk, Haldun Hadimioglu, Patrick Crowley ISBN 978-0120884766 0120884763
Original price was: $50.00.$35.00Current price is: $35.00.
Network Processor Design Volume 3 Issues and Practices 1st Edition by Mark A. Franklin, Peter Z. Onufryk, Haldun Hadimioglu, Patrick Crowley- Ebook PDF Instant Download/Delivery: 978-0120884766, 0120884763
Full download Network Processor Design Volume 3 Issues and Practices 1st Edition after payment
Product details:
ISBN 10: 0120884763
ISBN 13: 978-0120884766
Author: Mark A. Franklin, Peter Z. Onufryk, Haldun Hadimioglu, Patrick Crowley
The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors.
Through chapters on hardware, software, performance and modeling, Network Processor Design illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors.
Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.
Table of contents:
1. Network Processors: New Horizons
1.1 Architecture
1.2 Tools and Techniques
1.3 Applications
1.4 Conclusions
References
2. Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches
2.1 Instruction Delivery in NP Data Processors
2.1.1 Fixed-Size Control Store
2.1.2 Using a Cache as a Fixed-Size Control Store
2.2 Segmented Instruction Cache
2.2.1 Segment Sizing Strategies
Implementation
2.2.3 Address Mapping
2.2.4 Enforcing Instruction Memory Bandwidth Limits
2.3 Experimental Evaluation
2.3.1 Benchmark Programs and Methodology
2.3.2 Segment Sizing
2.3.3 Sources of Conflict Misses
2.3.4 Profile-Driven Code Scheduling to Reduce Misses
2.3.5 Using Set-Associativity to Reduce Misses
2.3.6 Segment Sharing
2.4 Related Work
2.5 Conclusions and Future Work
References
3. Efficient Packet Classification with Digest Caches
3.1 Related Work
3.2 Our Approach
3.2.1 The Case for an Approximate Algorithm
3.2.2 Dimensioning a Digest Cache
3.2.3 Theoretical Comparison
3.2.4 A Specific Example of a Digest Cache
3.2.5 Exact Classification with Digest Caches
3.3 Evaluation
3.3.1 Reference Cache Implementations
3.3.2 Results
3.4 Hardware Overhead
3.4.1 IXP Overhead
3.4.2 Future Designs
3.5 Conclusions
Acknowledgments
References
4. Towards a Flexible Network Processor Interface for RapidIO, HyperTransport, and PCI-Express
4.1 Interface Fundamentals and Comparison
4.1.1 Functional Layers
4.1.2 System Environment
4.1.3 Common Tasks
4.2 Modeling the Interfaces
4.2.1 Click for Packet-Based Interfaces
4.2.2 PCI Express
4.2.3 RapidIO
4.2.4 HyperTransport
4.3 Architecture Evaluation
4.3.1 Micro-Architecture Model
4.3.2 Simplified Instruction Set with Timing
4.3.3 Mapping and Implementation Details
4.3.4 Profiling Procedure
5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet
5.1 Requirements on TCP Offload Solution
5.2 Architecture of TOE Solution
5.2.1 Architecture Details
5.2.2 TCP-Aware Hardware Multithreading and Scheduling Logic
5.3 Performance Analysis
5.4 Conclusions
Acknowledgments
References
6. A Hardware Platform for Network Intrusion Detection and Prevention
6.1 Design Rationales and Principles
6.1.1 Motivation for Hardware-Based NNIDS
6.1.2 Characterization of NIDS Components
6.1.3 Hardware Architecture Considerations
6.2 Prototype NNIDS on a Network Interface
6.2.1 Hardware Platform
6.2.2 Snort Hardware Implementation
6.2.3 Network Interface to Host
6.2.4 Pattern Matching on the FPGA Coprocessor
6.2.5 Reusable IXP Libraries
6.3 Evaluation and Results
6.3.1 Functional Verification
8. Design Details and Challenges
8.3 Design Details and Challenges
8.3.1 Baker: A Domain-Specific Programming Language
8.3.2 Profile-Guided, Automated Mapping Compiler
8.3.3 Runtime System
8.4 Conclusions
References
9. RNOS – A Middleware Platform for Low-Cost Packet-Processing Devices
9.1 Scenario
9.2 Analysis Model of RNOS
9.2.1 Application Model
9.2.2 Input Model – SLA, Flows, and Microflows
9.2.3 Resource Model
9.2.4 Calculus
9.3 Implementation Model of RNOS
9.3.1 Path-Threads
9.3.2 Scheduler
9.3.3 Implementation
9.4 Measurements and Comparison
9.5 Conclusions and Outlook
Acknowledgments
References
10. On the Feasibility of Using Network Processors for DNA Queries
10.1 Architecture
10.1.1 Scoring and Aligning
10.1.2 Hardware Configuration
10.1.3 Software Architecture
10.1.4 Aho-Corasick
10.1.5 Nucleotide Encoding
10. On the Feasibility of Using Network Processors for DNA Queries
Tác giả: Herbert Bos, Kaiming Huang
10.1 Architecture
10.1.1 Scoring and Aligning
10.1.2 Hardware Configuration
10.1.3 Software Architecture
10.1.4 Aho-Corasick
10.1.5 Nucleotide Encoding
10.2 Implementation Details
10.3 Results
10.4 Related Work
10.5 Conclusions
Acknowledgments
References
11. Pipeline Task Scheduling on Network Processors
11.1 The Pipeline Task Assignment Problem
11.1.1 Notation and Assignment Constraints
11.1.2 Performance Metrics
11.1.3 Related Work
11.2 The Greedypipe Algorithm
11.2.1 Basic Idea
11.2.2 Overall Algorithm
11.2.3 Greedypipe Performance
11.3 Pipeline Design with Greedypipe
11.3.1 Number of Pipeline Stages
11.3.2 Sharing of Tasks Between Flows
11.3.3 Task Partitioning
11.4 A Network Processor Problem
11.4.1 Longest Prefix Matching (LPM)
11.4.2 AES Encryption – A Pipelined Implementation
11.4.3 Data Compression – A Pipelined Implementation
11.4.4 Greedypipe NP Example Design Results
11.5 Conclusions
Acknowledgments
References
12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs
12.1 Related Work
12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs
Tác giả: Matthias Grünewald, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert
12.1 Related Work
12.2 Modeling Packet-Processing Systems
12.2.1 Flow Processing Graph
12.2.2 SoC Architecture
12.3 Scheduling
12.3.1 Forwarding Flow Segments Between PES
12.3.2 Processing Flow Segments in PEs
12.3.3 A Scheduling Example
12.4 Mapping the Application to the System
12.5 Estimating the Resource Consumption
12.6 A Design Space Exploration Example
12.6.1 Application and System Parameters
12.6.2 Results
12.7 Conclusions
Acknowledgments
References
13. Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures
Tác giả: Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
13.1 Related Work
13.2 Application Analysis
13.2.1 Static vs. Dynamic Analysis
13.2.2 Annotated Directed Acyclic Graphs
13.2.3 Application Parallelism and Dependencies
13.2.4 ADAG Reduction
13.3 ADAG Clustering Using Maximum Local Ratio Cut
13.3.1 Clustering Problem Statement
13.3.2 Ratio Cut
13.3.3 Maximum Local Ratio Cut
13.3.4 MLRC Complexity
13.4 ADAG Results
13.4.1 The Packet Bench Tool
13.4.2 Applications
13.4.3 Basic Block Results
13. Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures
Tác giả: Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
13.4.4 Clustering Results
13.4.5 Application ADAGs
13.4.6 Identification of Coprocessor Functions
13.5 Mapping Application DAGs to NP Architectures
13.5.1 Problem Statement
13.5.2 Mapping Algorithm
13.5.3 Mapping and Scheduling Results
13.6 Conclusions
References
People also search for:
network processor design volume
network design process
network processor vs cpu
network design principles cisco
network design and configuration
Tags: Mark Franklin, Peter Onufryk, Haldun Hadimioglu, Patrick Crowley, Network Processor, Design Volume 3