CAD of Circuits and Integrated Systems 1st Edition by Ali Mahdoum – Ebook PDF Instant Download/Delivery: 978-1786305978, 1786305976
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Product details:
ISBN 10: 1786305976
ISBN 13: 978-1786305978
Author: Ali Mahdoum
Table of contents:
Chapter 1. Basic Notions on Computational Complexity and Approximate Techniques
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Computational complexity
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Introduction
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Big O notation
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Ω Notation
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Calculation of T(n)
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Language computability
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Turing machine and class P
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Non-deterministic algorithm and class NP
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NP-complete problems
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NP-hard problems
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NP-intermediate problems
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Co-NP problems
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Class hierarchy
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Heuristics and metaheuristics
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Definitions
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Graph theory
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Branch and bound technique
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Tabu search technique
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Simulated annealing technique
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Genetic and evolutionary algorithms
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Conclusion
Chapter 2. Basic Notions on the Design of Digital Circuits and Systems
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Introduction
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History of VLSI circuit design
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Prediffused circuit
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Sea of gates
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Field-programmable gate array (FPGA)
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Elementary pre-characterized circuit (standard cells)
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Full-custom circuit
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Silicon compilation
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System design level
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Synthesis
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Floorplanning
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Analysis
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Verification
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Register transfer design level
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Synthesis
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Analysis
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Verification
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Module design level
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Synthesis
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Analysis
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Verification
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Gate design level
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Synthesis
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Analysis
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Verification
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Transistor level
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NMOS and CMOS technologies
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Theory of MOS transistor (current IDS)
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Transfer characteristics of the inverter
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Static analysis of the inverter
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Threshold voltage of the inverter
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Estimation of rise and fall times of a capacitor
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Interconnections
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Synthesis of interconnections
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Synthesis of networks-on-chip
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Conclusion
Chapter 3. Case Study: Application of Heuristics and Metaheuristics in the Design of Integrated Circuits and Systems
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Introduction
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System level
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Synthesis of systems-on-chip (SoCs) with low energy consumption
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Heuristic application to dynamic voltage and frequency scaling (DVFS) for real-time systems under energy constraint
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Register transfer level
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Integer linear programming for scheduling operations of a data flow graph (DFG)
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Scheduling operations in a controlled DFG (speed–power tradeoff)
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Efficient code assignment to states of a finite state machine
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Synthesis of submicron transistors and interconnections for high-performance circuits under power, time, and surface constraints
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Module level
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Design of low-power digital circuits
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Reduction of memory access time for embedded systems
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Gate level
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Estimation of average and maximal power consumption
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Automated layout generation of regular structures (shifters, address decoders, PLAs)
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Automated layout generation according to River PLA technique
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Interconnections
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Low-power buffer insertion for submicron interconnections
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Data encoding/decoding for low-power submicron interconnections
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High-level synthesis of networks-on-chip under bandwidth, surface, and power constraints
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