Customizable Embedded Processors Design Technologies and Applications Systems on Silicon 1st Edition by Paolo Ienne, Rainer Leupers ISBN 978-0123695260 0123695260
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ISBN 10: 0123695260
ISBN 13: 978-0123695260
Author: Paolo Ienne, Rainer Leupers
Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization.
This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include “as is in their products; but rather, to build sound methodologies to tailor-fit processors to the specific needs of such products. This book addresses the goal of maintaining a very large family of processors, with a wide range of features, at a cost comparable to that of maintaining a single processor.
- First book to present comprehensively the major ASIP design methodologies and tools without any particular bias
- Written by most of the pioneers and top international experts of this young domain
- Unique mix of management perspective, technical detail, research outlook, and practical implementation
Table of contents:
Part I: Opportunities and Challenges
1 From Ready-to-Wear to Tailor-Made Paolo Ienne and Rainer Leupers
1.1 The Call for Flexibility
1.2 Cool Chips for Shallow Pockets
1.3 A Million Processors for the Price of One?
1.4 Processors Coming of Age
1.5 This Book.
1.6 Travel Broadens the Mind
2 Opportunities for Application-Specific Processors: The Case of Wireless Communications
Gerd Ascheid and Heinrich Meyr
2.1 Future Mobile Communication Systems
2.2 Heterogeneous MPSoC for Digital Receivers
2.2.1 The Fundamental Tradeoff between Energy Efficiency and Flexibility
How to Exploit the Huge Design Space?
2.2.3 Canonical Receiver Structure
2.2.4 Analyzing and Classifying the Functions of a Digital Receiver
2.2.5 Exploiting Parallelism
2.3 ASIP Design
2.3.1 Processor Design Flow
2.3.2 Architecture Description Language Based Design
2.3.3 Too Much Automation Is Bad
2.3.4 Processor Design: The LISATek Approach
2.3.5 Design Competence Rules the World..
2.3.6 Application-Specific or Domain-Specific Processors?
3 Customizing Processors: Lofty Ambitions, Stark Realities
Joseph A. Fisher, Paolo Faraboschi, and Cliff Young
3.1 The “CFP” project at HP Labs
3.2 Searching for the Best Architecture Is Not a Machine-Only Endeavor
3.3 Designing a CPU Core Still Takes a Very Long Time
3.4 Don’t Underestimate Competitive Technologies.
3.5 Software Developers Don’t Always Help You
3.6 The Embedded World Is Not Immune to Legacy Problems
3.7 Customization Can Be Trouble
3.8 Conclusions.
Part II: Aspects of Processor Customization
4 Architecture Description Languages
Prabhat Mishra and Nikil Dutt
4.1 ADLs and other languages.
4.2 Survey of Contemporary ADLs
4.2.1 Content-Oriented Classification of ADLS
4.2.2 Objective-Based Classification of ADLs
4.3 Conclusions.
5 C Compiler Retargeting Rainer Leupers
5.1 Compiler Construction Background.
5.1.1 Source Language Frontend
5.1.2 Intermediate Representation and Optimization
5.1.3 Machine Code Generation
5.2 Approaches to Retargetable Compilation.
5.2.1 MOBILE
5.2.2 GNU C Compiler
Contents
5.2.3 Little C Compiler
5.2.4 CoSy
5.3 Processor Architecture Exploration
5.3.1 Methodology and Tools for ASIP Design
5.3.2 ADL-Based Approach
C Compiler Retargeting in the LISATek Platform
5.4.1 Concept.
5.4.2 Register Allocator and Scheduler
5.4.3 Code Selector
5.4.4 Results
5.5 Summary and Outlook
6 Automated Processor Configuration and Instruction Extension
David Goodwin, Steve Leibson, and Grant Martin
6.1 Automation Is Essential for ASIP Proliferation
6.2 The Tensilica Xtensa LX Configurable Processor
6.3 Generating ASIPs Using Xtensa
6.4 Automatic Generation of ASIP Specifications
6.5 Coding an Application for Automatic ASIP Generation
6.6 XPRES Benchmarking Results
6.7 Techniques for ASIP Generation
6.7.1 Reference Examples for Evaluating XPRES
6.7.2
VLIW-FLIX: Exploiting Instruction Parallelism
6.7.3 SIMD (Vectorization): Exploiting Data Parallelism
6.7.4 Operator Fusion: Exploiting Pipeline Parallelism
6.7.5 Combining Techniques
6.8 Exploring the Design Space.
6.9.1 Application Performance Estimation.
6.9 Evaluating Xpres Estimation Methods
6.9.2 ASIP Area Estimation
6.9.3 Characterization Benchmarks
6.9.4 Performance and Area Estimation
6.10 Conclusions and Future of the Technology
7 Automatic Instruction-Set Extensions Laura Pozzi and Paolo Ienne
7.1 Beyond Traditional Compilers
7.1.1 Structure of the Chapter
7.2 Building Block for Instruction Set Extension
7.2.1 Motivation
7.2.2 Problem Statement: Identification and Selection
7.2.3 Identification Algorithm
7.2.4 Results
7.3 Heuristics
7.3.1 Motivation
7.3.2 Types of Heuristic Algorithms
7.3.3 A Partitioning-Based Heuristic Algorithm.
7.3.4 A Clustering Heuristic Algorithm
7.4 State-Holding Instruction-Set Extensions
7.4.1 Motivation
7.4.2 Local-Memory Identification Algorithm
7.4.3 Results
7.5 Exploiting Pipelining to Relax I/O Constraints
7.5.1 Motivation
7.5.2 Reuse of the Basic Identification Algorithm
7.5.3 Problem Statement: Pipelining
7.5.4 1/0 Constrained Scheduling Algorithm
7.5.5 Results
7.6 Conclusions and Further Challenges
8 Challenges to Automatic Customization Nigel Topham
8.1 The ARCompactTM Instruction Set Architecture
8.1.1 Mechanisms for Architecture Extension
8.1.2 ARCompact Implementations
8.2 Microarchitecture Challenges.
8.3 Case Study-Entropy Decoding
8.3.1 Customizing VLD Extensions
8.4 Limitations of Automated Extension
8.5 The Benefits of Architecture Extension
8.5.1 Customization Enables CoDesign.
8.5.2 Customization Offers Performance Headroom
8.5.3 Customization Enables Platform IP
8.5.4 Customization Enables Differentiation
8.6 Conclusions.
9 Coprocessor Generation from Executable Code Richard Taylor and David Stewart
9.1 Introduction
9.2 User Level Flow
9.3 Integration with Embedded Software
9.4 Coprocessor Architecture
9.5 ILP Extraction Challenges
9.6 Internal Tool Flow
9.7 Code Mapping Approach
9.8 Synthesizing Coprocessor Architectures
9.9 A Real-World Example
9.10 Summary
10 Datapath Synthesis Philip Brisk and Majid Sarrafzadeh
10.1 Introduction
10.2 Custom Instruction Selection
10.3 Theoretical Preliminaries
10.3.1 The Minimum Area-Cost Acyclic Common Supergraph Problem
10.3.2 Subsequence and Substring Matching Techniques
10.4 Minimum Area-Cost Acyclic Common Supergraph Heuristic
10.4.1 Path-Based Resource Sharing
10.4.2 Example
10.4.3 Pseudocode
10.5 Multiplexer Insertion
10.5.1 Unary and Binary Noncommutative Operators
10.5.2 Binary Commutative Operators
10.6 Datapath Synthesis
10.6.1 Pipelined Datapath Synthesis
10.6.2 High-Level Synthesis
10.7 Experimental Results.
10.8 Conclusion
11 Instruction Matching and Modeling Sri Parameswaran, Jörg Henkel, and Newton Cheung
11.1 Matching Instructions
11.1.1 Introduction to Binary Decision Diagrams
11.1.2 The Translator
11.1.3 Filtering Algorithm
11.1.4 Combinational Equivalence Checking Model..
11.1.5 Results
11.2 Modeling
11.2.1 Overview
11.2.2 Customization Parameters
11.2.3 Characterization for Various Constraints
11.2.4 Equations for Estimating Area, Latency, and Power Consumption
11.2.5 Evaluation Results
11.3 Conclusions.
12 Processor Verification Daniel Große, Robert Siegmund, and Rolf Drechsler
12.1 Motivation
12.2 Overview of Verification Approaches
12.2.1 Simulation
12.2.2 Semiformal Techniques
12.2.3 Proof Techniques
12.2.4 Coverage
.12.3 Formal Verification of a RISC CPU
12.3.1 Verification Approach
12.3.2 Specification.
12.3.3 SystemC Model
12.3.4 Formal Verification
12.4 Verification Challenges in Customizable and Configurable Embedded Processors
12.5 Verification of Processor Peripherals
12.5.1 Coverage-Driven Verification Based on Constrained-Random Stimulation
12.5.2 Assertion-Based Verification of Corner Cases
12.5.3 Case Study: Verification of an On-Chip
Bus Bridge
12.6 Conclusions.
13 Sub-RISC Processors Andrew Mihal, Scott Weber, and Kurt Keutzer
13.1 Concurrent Architectures, Concurrent Applications
13.2 Motivating Sub-RISC PES
13.2.1 RISC PES
13.2.2 Customizable Datapaths
13.2.3 Synthesis Approaches
13.2.4 Architecture Description Languages
13.3 Designing TIPI Processing Elements
13.3.1 Building Datapath Models
13.3.2 Operation Extraction
13.3.3 Single PE Simulator Generation
13.3.4 TIPI Multiprocessors
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Tags: Paolo Ienne, Rainer Leupers, Customizable Embedded, Processors Design, Applications Systems