(Ebook PDF) Digital Design Basic Concepts and Principles 1st Edition by Mohammad Karim, Xinghao Chen ISBN 9781351834957 1351834959 full chapters

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ISBN 10:1351834959

ISBN 13:9781351834957,

Author: Mohammad Karim; Xinghao Chen

In today’s digital design environment, engineers must achieve quick turn-around time with ready accesses to circuit synthesis and simulation applications. This type of productivity relies on the principles and practices of computer aided design (CAD). Digital Design: Basic Concepts and Principles addresses the many challenging issues critical to today’s digital design practices such as hazards and logic minimization, finite-state-machine synthesis, cycles and races, and testability theories while providing hands-on experience using one of the industry’s most popular design application, Xilinx Web PACK™. The authors begin by discussing conventional and unconventional number systems, binary coding theories, and arithmetic as well as logic functions and Boolean algebra. Building upon classic theories of digital systems, the book illustrates the importance of logic minimization using the Karnaugh map technique. It continues by discussing implementation options and examining the pros and cons of each method in addition to an assessment of tradeoffs that often accompany design practices. The book also covers testability, emphasizing that a good digital design must be easy to verify and test with the lowest cost possible. Throughout the text, the authors analyze combinational and sequential logic elements and illustrate the designs of these components in structural, hierarchical, and behavior VHDL descriptions. Coveringfundamentals and best practices, Digital Design: Basic Concepts and Principles provides you with critical knowledge of how each digital component ties together to form a system and develops the skills you need to design and simulate these digital components using modern CAD software.

Table of Contents:

• 1 Data Type and Representations
• 1.1 Introduction
• 1.2 Positional Number Systems
• 1.3 Number System Conversions
• 1.3.1 Integer Conversion
• 1.3.2 Conversion of Fractions
• 1.4 Negative Numbers
• 1.5 Binary Arithmetic
• 1.6 Unconventional Number Systems
• 1.7 Binary Codes
• 1.8 Error-Detecting and Correcting Codes
• 1.9 CAD System
• 1.10 Summary
• Problems
• 2 Boolean Algebra
• 2.1 Introduction
• 2.2 Logic Operations
• 2.2.1 AND Function
• 2.2.2 OR Function
• 2.2.3 NOT Function
• 2.2.4 NAND Function
• 2.2.5 NOR Function
• 2.2.6 Exclusive-OR and Exclusive-NOR Functions
• 2.3 Logic Functions from Truth Table
• 2.4 Boolean Algebra
• 2.5 Summary
• Problems
• 3 Minimization of Logic Functions
• 3.1 Introduction
• 3.2 Karnaugh Map
• 3.3 Incompletely Specified Functions in K-Maps
• 3.4 K-Maps for POS Form of Functions
• 3.5 Map-Entered Variables
• 3.6 Hazards
• 3.7 Single-Output Q-M Tabular Reduction
• 3.8 Multiple-Output Q-M Tabular Reduction
• 3.9 Summary
• Problems
• 4 Logic Function Implementations
• 4.1 Introduction
• 4.2 Functionally Complete Operation Sets
• 4.3 NAND- and NOR-Only Implementations
• 4.4 Function Implementation Using XORs and ANDs
• 4.5 Circuit Implementation Using Gate Arrays
• 4.6 Logic Function Implementation Using Multiplexers
• 4.7 Logic Function Implementation Using Demultiplexers and Decoders
• 4.8 Logic Function Implementation Using ROMs
• 4.9 Logic Function Implementation Using PLDs
• 4.9.1 PROMs
• 4.9.2 PLAs
• 4.9.3 PALs
• 4.9.4 PLD Highlights
• 4.10 Logic Function Implementation Using Threshold Logic
• 4.11 Logic Function Implementation Using Transmission Gates
• 4.12 Summary
• Problems
• 5 Introduction to VHDL
• 5.1 Introduction
• 5.2 VHDL Programming Environment
• 5.3 Structural VHDL
• 5.4 Functional VHDL
• 5.5 Behavioral VHDL
• 5.6 Hierarchical VHDL
• 5.7 Logic Circuit Synthesis with Xilinx WebPACK ISE Project Navigator
• 5.8 Simulation of Timing Characteristics
• 5.9 Logic Circuit Implementation with FPGA Device
• 5.10 Summary
• Problems
• 6 Design of Modular Combinatorial Components
• 6.1 Introduction
• 6.2 Special-Purpose Decoders and Encoders
• 6.3 Code Converters
• 6.4 Error-Detecting and Error-Correcting Circuits
• 6.5 Biliary Arithmetic
• 6.6 Binary Subtraction
• 6.7 High-Speed Addition
• 6.8 BCD Arithmetic
• 6.9 Comparators
• 6.10 Combinational Circuit Design Using VHDL
• 6.11 Arithmetic Logic Unit
• 6.12 ALU Design Using VHDL
• 6.13 Summary
• Problems
• 7 Sequential Logic Elements
• 7.1 Introduction
• 7.2 Latches
• 7.3 Set-Reset Flip-Flop
• 7.4 JK Flip-Flop
• 7.5 Master-Slave Flip-Flop
• 7.6 Edge-Triggered Flip-Flops
• 7.7 Delay and Trigger Flip-Flops
• 7.8 Monostable Flip-Flop
• 7.9 Design of Sequential Elements Using VHDL
• 7.10 Sequential Circuits
• 7.11 Summary
• Problems
• 8 Synchronous Sequential Circuits
• 8.1 Introduction
• 8.2 Formalism
• 8.3 Mealy and Moore Models
• 8.4 Analysis of Sequential Circuits
• 8.5 Equivalent States
• 8.6 Incompletely Specified Sequential Circuits
• 8.7 State Assignments
• 8.8 Design Algorithm
• 8.9 Synchronous Sequential Circuit Implementation Using VHDL
• 8.10 Summary
• Problems
• 9 Design of Modular Sequential Components
• 9.1 Introduction
• 9.2 Synchronous Counters
• 9.3 Registers
• 9.4 Shift Registers as Counters
• 9.5 Counter and Register Applications
• 9.6 Register Transfer Language
• 9.7 Registers and Counters in VHDL
• 9.8 Summary
• Problems
• 10 Synchronous Arithmetic
• 10.1 Introduction
• 10.2 Serial Adder/Subtractor
• 10.3 Serial-Parallel Multiplication
• 10.4 Fast Multiplication
• 10.5 Implementation of Sequential Arithmetic Using VHDL
• 10.6 Summary
• Problems
• 11 Asynchronous Sequential Circuits
• 11.1 Introduction
• 11.2 Pulse-Mode Circuit
• 11.3 Fundamental Mode Circuits
• 11.4 Cycles, Races, and Hazards
• 11.5 Fundamental-Mode Outputs
• 11.6 Summary
• Problems
• 12 Introduction to Testability
• 12.1 Introduction
• 12.2 Controllability and Observability
• 12.3 Deterministic Testability versus Random Testability
• 12.4 Test of Integrated Circuits
• 12.5 Fault Models
• 12.6 Test Sets and Test Generation
• 12.7 Topology-Based Testability Analysis
• 12.8 Simulation-Based Testability Analysis
• 12.9 Fault Analysis and Fault-Based Testability Analysis
• 12.10 Testability Metrics
• 12.11 Design-for-Testability
• 12.12 Summary

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Digital Design,Mohammad Karim,Xinghao Chen,Basic Concepts,Principles