Advanced Microprocessors Peripherals 3rd Edition by Bhurchandi ISBN 978-1259006135 1259006131
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Product details:
ISBN 10: 1259006131
ISBN 13: 978-1259006135
Author: K. M. Bhurchandi
Table of contents:
Chapter 1: The Processors: 8086/8088- Architectures, Pin Diagrams and Timing Diagrams
1.1 Register Organisation of 8086
1.2 Architecture
1.3 Signal Descriptions of 8086
1.4 Physical Memory Organisation
1.5 General Bus Operation
1.6 I/O Addressing Capability
1.7 Special Processor Activities
1.8 Minimum Mode 8086 System and Timings
1.9 Maximum Mode 8086 System and Timings
1.10 The Processor 8088
Summary Exercises
Chapter 2: 8086/8088 Instruction Set and Assembler Directives
2.1 Machine Language Instruction Formats
2.2 Addressing Modes of 8086
2.3 Instruction Set of 8086/8088
2.4 Assembler Directives and Operators
2.5 Do’s and Don’ts While Using Instructions
Summary Exercises
Chapter 3: The Art of Assembly Language Programming with 8086/8088
3.1 A Few Machine Level Programs
3.2 Machine Coding the Programs
3.3 Programming with an assembler
3.4 Assembly Language Example Programs Summary Exercises
Chapter 4: Special Architectural Features and Related Programming
4.1 Introduction to Stack
4.2 Stack Structure of 8086/88
4.3 Interrupts and Interrupt Service Routines
4.4 Interrupt Cycle of 8086/8088
4.5 Non Maskable Interrupt
4.6 Maskable Interrupt (INTR)
4.7 Interrupt Programming
4.8 Passing Parameters To Procedures
4.9 Handling Programs of Size More than 64 K
4.10 MACROS
4.11 Timings and Delays
Summary
Exercises
Chapter 5: Basic Peripherals and their Interfacing with 8086/88
5.1 Semiconductor Memory Interfacing
5.2 Dynamic RAM Interfacing
5.3 Interfacing I/O Ports
5.4 PIO 8255 [Programmable Input-Output Port]
5.5 Modes of Operation of 8255
5.6 Interfacing Analog to Digital Data Converters
5.7 Interfacing Digital to Analog Converters
5.8 Stepper Motor Interfacing
5.9 Control of High Power Devices Using 8255
Summary
Exercises
Chapter 6: Special Purpose Programmable Peripheral Devices and Their Interfacing
6.1 Programmable Interval Timer 8254
6.2 Programmable Interrupt Controller 8259A
6.3 The Keyboard/Display Controller 8279
6.4 Programmable Communication Interface 8251 USART
Summary
Exercises
Chapter 7: DMA, & High Storage Capacity Memory Devices
7.1 DMA Controller 8257
7.2 DMA Transfers and Operations
7.3 Programmable DMA Interface 8237
7.4 High Storage Capacity Memory Devices
10.7 Protected Mode of 80386
10.8 Segmentation
10.9 Paging
10.10 Virtual 8086 MODE
10.11 Enhanced Instruction Set of 80386
10.12 The Coprocessor 80387
10.13 The CPU With a Numeric Coprocessor-80486DX
Summary
Exercises
Chapter 8: Multimicroprocessor Systems
8.1 Interconnection Topologies
8.2 Software Aspects of Multimicroprocessor Systems
8.3 Numeric Processor 8087
8.4 I/O Processor 8089
8.5 Bus Arbitration and Control
8.6 Tightly Coupled and Loosely Coupled Systems
8.7 Design of a PC Based Multimicroprocessor System
Summary
Exercises
Chapter 9: 80286-80287-A Microprocessor with Memory Management and
Protection
9.1 Salient Features of 80286
9.2 Internal Architecture of 80286
9.3 Signal Descriptions of 80286
9.4 Real Addressing Mode
9.5 Protected Virtual Address Mode (PVAM)
9.6 Privilege
9.7 Protection
9.8 Special Operations
9.9 80286 Bus Interface
9.10 Basic Bus Operations
9.11 Fetch Cycles of 80286
9.12 80286 Minimum System Configuration
9.13 Interfacing Memory and I/O Devices with 80286
9.14 Priority of Bus Use by 80286
9.15 Bus Hold and HLDA Sequence
9.16 Interrupt Acknowledge Sequence
9.17 Instruction Set Features
9.18 80287 Math Coprocessor
Summary
Exercises
Chapter 10: 80386-80387 and 80486-The 32-Bit Processors
10.1 Salient Features of 80386dx
10.2 Architecture and Signal Descriptions of 80386
10.3 Register Organization of 80386
10.4 Addressing Modes
10.5 Data Types of 80386
10.6 Real Address Mode of 80386
Activate
to Cottis
Chapter 11: Recent Advances in Microprocessor Architectures-A Journey from Pentium Onwards
11.1 Salient Features of 80586 (Pentium)
11.2 A Few Relevant Concepts of Computer Architecture
11.3 System Architecture
11.4 Branch Prediction
11.5 Enhanced Instruction Set of Pentium
11.6 What is MMX?
11.7 Intel MMX Architecture
11.8 MMX Data Types
11.9 Wraparound and Saturation Arithmetic
11.10 MMX Instruction Set
11.11 Salient Points about Multimedia Application Programming
11.12 Journey to Pentium-Pro and Pentium-II
11.13 Pentium III (P-III)-The CPU of the Next Millennium
Summary
Exercises
Chapter 12: Pentium 4-Processor of the New Millennium
12.1 Genesis of Birth of Pentium 4
12.2 Salient Features of Pentium 4
12.3 Netburst Microarchitecture for Pentium 4
12.4 Instruction Translation Lookaside Buffer (ITLB) and Branch Prediction
12.5 Why out of order Execution
12.6 Rapid Execution Module
12.7 Memory Subsystem
12.8 Hyperthreading Technology
12.9 Hyperthreading in Pentium
12.10 Extended Instruction Set in Advanced Pentium Processors
12.11 Instruction Set Summary
12.12 Need for Formal Verification
Summary
Activate Go to Setting
Exercises
Chapter 13: RISC Architecture-An Overview
13.1 A Short History of RISC Processors
13.2 Hybrid Architecture-RISC and Cisc Convergence
13.3 The Advantages of RISC
13.4 Basic Features of RISC Processors
13.5 Design Issues of RISC Processors
13.6 Performance Issues in Pipelined Systems
13.7 Architecture of Some RISC Processors
13.8 Discussion on Some RISC Architectures Summary
Exercises
Chapter 14: Microprocessor-Based Aluminium Smelter Control
14.1 General Process Description of an Aluminium Smelter
14.2 Normal Control of Electrolysis Cell
14.3 Cell Abnormalities on an Aluminium Smelter
14.4 Brief Description of the Control Laws for Abnormal Cells
14.5 Salient Issues in Design
14.6 Smelter Controller Hardware
14.7 Control Algorithm Summary
Chapter 15: Design of a Microprocessor Based Pattern Scanner System
15.1 Organization of the Scanner System
15.2 Description of the Scanning System
15.3 Programmed Mode of Operation
15.4 Memory Read/Write System and Start-Up Procedures
15.5 Result and Discussion Summary
Chapter 16: Design of an Electronic Weighing Bridge
16.1 Design Issues
16.2 Software Development Summary
Chapter 17: An Introduction to Architecture and Programming 8051 and 80196
17.1 Intel’s Family of 8-Bit Microcontrollers
17.2 Architecture of 8051
17.3 Signal Descriptions of 8051
17.4 Register Set of 8051
Activate
17.5 Important Operational Features of 8051-Programme Status Word (PSW)
Go to Setting
17.6 Memory and I/O Addressing by 8051
17.7 Interrupts and Stack of 8051
17.8 Addressing Modes of 8051
17.9 8051 Instruction Set
17.10 Programming Examples
11.17 Intel’s16-Bit Microcontroller Family MCS-96
Summary
Exercises
Chapter 18: 8051 Peripherals Interfacing
18.1 Interfacing with 8051 Ports
18.2 Designing with on Chip Timers
18.3 Interrupt Structure of 8051
18.4 Serial Communication Unit
18.5 Power Control Register (PCON-SFR ADD 87H)
18.6 Design of a Microcontroller 8051 Based Length Measurement System for Continuously Rollingcloth or Paper
Summary
Exercises
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